Programmable integrated circuit (IC) devices such as field programmable gate array (FPGA) devices may include logic elements that can be configured to perform any of a variety of functions. A common feature of most FPGA devices, known as partial reconfiguration, further allows a subset of logic elements in the FPGA to be dynamically reconfigured while the remaining logic elements continue to operate undisturbed. As such, predefined regions or logic elements in the device may be updated without disrupting applications running in other parts of the device.
Generally, a circuit designer may use an electronic design automation (EDA) or computer-aided design (CAD) tool to create a design for an IC device. If the IC device is a programmable device (e.g., an FPGA device), the circuit designer may specify specific regions on the device as partial reconfiguration regions. When the design is compiled, the EDA tool may generate a full-chip configuration bitstream and a partial configuration bitstream for each of the specified partial reconfiguration regions.
Typically, the circuit designer may perform an initial full-chip configuration by downloading the full-chip configuration bitstream to the device. The circuit designer may then use the partial configuration bitstream(s) generated by the EDA tool to reconfigure the predefined partial reconfiguration region(s) on the device at a later time without affecting other regions in the device (e.g., non-partial reconfiguration region in the device may continue to operate while the predefined regions are being reconfigured).
However, as a different partial configuration bitstream is generated for each partial reconfiguration region, the circuit designer may need to keep track of a high number of different partial configuration bitstream files. As an example, if there are ten partial reconfiguration regions in the design, the EDA tool may generate ten different partial configuration bitstream files. Additionally, the circuit designer may only reconfigure a single reconfiguration region in the device at any one time. As such, when multiple partial reconfiguration regions on the device need to be updated at a later time, each partial reconfiguration region needs to be updated individually using its own partial configuration bitstream.
It is within this context that the embodiments described herein arise.